1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits and semiconductor devices and, more particularly, to the formation of contacts to semiconductor bulk substrates of SOI devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors (FETs), wherein, for many types of complex circuitry, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of N-channel transistors and P-channel transistors are formed on a substrate including a crystalline semiconductor layer.
Nowadays, FETs are usually built on silicon-on-insulator (SOI) substrates and in particular Fully Depleted silicon-on-insulator (FDSOI) substrates. The channels of the FETs are formed in thin semiconductor layers, typically including or made of silicon material or other semiconductor materials, wherein the semiconductor layers are formed on insulating layers, buried oxide (BOX) layers, that are formed on semiconductor bulk substrates. One severe problem caused by the aggressive downscaling of the semiconductor devices must be seen in the occurrence of leakage currents. Since leakage currents depend on the threshold voltages of the FETs, substrate biasing (back biasing) can reduce leakage power. With this advanced technique, the substrate or the appropriate well is biased to raise the transistor thresholds, thereby reducing leakage currents. In PMOS devices, the body of the transistor is biased to a voltage higher than the positive supply voltage VDD. In NMOS devices, the body of the transistor is biased to a voltage lower than the negative supply voltage VSS.
FIG. 1a shows an SOI configuration with a semiconductor bulk substrate 10 wherein an N+ doped region 11 and a P+ doped region 12 are formed in the bulk substrate 10. Further, the SOI configuration comprises a BOX layer 13 formed on the semiconductor bulk substrate 10 and a semiconductor layer 20 formed on the BOX layer 13 and providing a channel region. FIG. 1a also depicts a layer of gate electrode material 14, e.g., polysilicon formed above semiconductor layer 20. The N+ doped region 11 and the P+ doped region 12 are used for back biasing of P-channel FET gates or N-channel FET gates, respectively. In integrated circuits (IC), cell structures are formed by gate electrode lines (poly lines) 14a defining standard cells of active semiconductor devices as the one shown on FIG. 1a. In general, the polysilicon (poly) lines 14a (FIGS. 1b and 1e) run parallel to each other. It is noted that the gates of the FETs may comprise a metal material in addition to the poly material. In advanced ICs, the gate constructs are so small that, with current technologies, they cannot be manufactured as arbitrarily placed gates. Instead, a regular grid of poly lines 14a has to be manufactured consisting of parallel poly line shapes 14a with exactly defined width and spacing, as shown in FIG. 1b. Afterwards, in additional manufacturing steps, unwanted poly lines 14a will be removed using a poly line (PC) cut mask. The regular poly line grid (“sea of gates”) is required to be surrounded by boundary cells that contain parallel poly line shapes 15 of larger widths in order to protect the regular poly lines 14a of the standard cells against polishing defects during manufacturing.
In order to reduce the time required to perform the design process, cell libraries have been created wherein standard cell designs are available. Of course, there are applications that may require one or more specialized cells, in which case the designer will either create a custom cell for the layout or alter a library cell in a manner required by the desired design. The resulting layout is used to manufacture the desired integrated circuit. Depending on the used design and library, back biasing can be done for the PMOS or NMOS devices or both. To bias the bulk of the NMOS and PMOS of the standard cells, voltages are created by charge pumps, which are custom blocks that output VDDbias and VSSbias voltages. Each standard cell row must have at least one (body- or well-) tap cell. However, designers sometimes have a rule of one tap cell placed in a standard cell row per every certain distance at regular intervals.
Similar to the grid of standard cells, a grid of tap cells is commonly used in integrated circuit design to provide for the body bias of the transistors. The tap cells have to create electrical connections between a network providing biasing voltages and the P+/N+ regions as regions 11 and 12 shown in FIG. 1a. Since the biasing voltage network is implemented on metal layers that are routed several layers positioned above the BOX layer 13 shown in FIG. 1a and given that the P+/N+ regions 11 and 12 reside under the BOX layer 13 in the bulk substrate 10, parts of the BOX layer 13 (being a very good insulator) have to be removed in order to create contacts to the regions 11, 12. Since the BOX layer 13 is relatively thick, the openings to be etched into the BOX layer 13 have to be relatively large. Therefore, a particular problem arises in the conventional techniques, as illustrated in FIGS. 1c to 1e. 
FIG. 1c shows a configuration similar to the one shown in FIG. 1a wherein after patterning of the semiconductor layer 20 an opening is formed in the BOX layer 13 that is filled with the poly material layer 14 used for the formation of gate electrodes 14a of FETs. The opening of the BOX layer 13 is formed within the area of the regular poly line grid shown in FIG. 1b. The poly material layer 14 is formed after formation of the opening is formed in the box layer 13 for the formation of a back biasing contact. A mask layer 16 is formed above the poly material layer 14 as shown in FIG. 1c. As shown in FIG. 1d, the mask layer 16 is patterned by standard lithography to obtain a patterned mask 17 used to form poly lines (gates) 14a over the BOX layer 13 (see FIG. 1e).
However, during the etching process performed for creating the poly gates 14a, a thin poly ridge 19 is formed in the opening of the BOX layer 13. In fact, the formation of the poly ridge 19 cannot be properly controlled since focus of the employed lithography device lies on the positions where the poly gates 14a have to be formed. On the other hand, formation of the poly ridge 19 cannot be avoided due to the regular poly line grid formed. The undesired formation of the poly ridge 19 in the opening of the BOX layer 13 results in a pollution of the wafer since the unstable poly ridge structure 19 easily breaks off during the further processing.
In view of the situation described above, the present disclosure provides a technique of forming substrate contacts avoiding wafer pollution due to poly debris caused by the formation of thin poly ridges in large BOX openings in manufacturing processes of the art.